用verilog hdl编写十六进制转换十进制的程序

Question

如题所述

Answer 1

module BCD(clk,data,Ten,One);
input clk;
input[7:0] data;
output[3:0] Ten,One;
reg[3:0] Ten,One;
integer i;
always@ (posedge clk)
begin
Ten = 4'd0;
One = 4'd0;
for (i=6;i>=0;i=i-1)
begin
if (Ten >= 5) Ten = Ten + 3;
if (One >= 5) One = One + 3;
Ten = Ten << 1;
Ten[0] = One[3];
One = One << 1;
One[0] = data[i];
end
end
endmodule本回答被网友采纳

Answer 2

楼上的程序错了，到了十位就不能简单这么算了，因为产生十位的源数是十六进制的啊！