数字电路verilog HDL语言设计交通灯控制器

Question

数字电路verilog HDL语言设计交通灯控制器，要求如下

与现实中一般十字路口的交通灯功能一致，两条相交的道路优先级相同，通行时间相等(30秒~90秒，具体时间自行设定)
信号变换前3秒灯闪烁，具有倒计时显示功能
红灯到绿灯状态变换前应有等待另一方向通行结束的缓冲时间(各路口红灯同时亮3秒钟)
注解请尽量详细，希望借此学习hdl设计方式，邮箱：[email protected]

Answer 1

module LIGHT_CTRL(
clk , //sys clk 24mhz
rst_n , //n_reset

road_a_grn , //Road A Green
road_a_red , //Road A Red
road_b_grn , //Road B Green
road_b_red //Road B Red
);

//Input PIN
input clk ; //sys clk 24mhz
input rst_n ; //n_reset

//Output PIN
output road_a_grn ; //Road A Green
output road_a_red ; //Road A Red
output road_b_grn ; //Road B Green
output road_b_red ; //Road B Red

//Register And Wire
//1sec pulse
wire n_1s_cnt_end ;
wire n_500ms_pls ;
reg [31:0] r_cnt ;

//light ctrl state(1sec pls transition)
reg [2:0] r_state ;

//second cnt
reg [4:0] r_sec_cnt ;

//second cnt
reg r_blk_flg ;

//light output
wire n_road_a_grn ;
wire n_road_a_red ;
wire n_road_b_grn ;
wire n_road_b_red ;

reg road_a_grn ;
reg road_a_red ;
reg road_b_grn ;
reg road_b_red ;

//***RTL***
//1sec pulse and 500ms pulse
assign n_1s_cnt_end = (r_cnt == 32'h016E_35FF)? 1'b1 : 1'b0; //when cnt=23999999,1s pulse
assign n_500ms_pls = (r_cnt == 32'h00B7_1AFF)? 1'b1 : 1'b0; //when cnt=11999999,500ms pulse

always @(posedge clk or negedge rst_n) begin
if (~rst) begin
r_cnt <= 32'h0000_0000;
end
else begin
if(n_1s_cnt_end == 1'b1)
r_cnt <= 32'h0000_0000;
else
r_cnt <= r_cnt + 1'b1;
end
end

//light ctrl state(1sec pls transition)
//1st 24sec:00
//1st 3sec :10
//2nd 3sec :11
//others :goto 00
always @(posedge clk or negedge rst_n) begin
if (~rst) begin
r_state <= 3'b000;
end
else begin
if(n_1s_cnt_end == 1'b1)
if((r_state[1:0] == 2'b00) && (r_sec_cnt == 5'b1_0111)
r_state <= {r_state[2],2'b10};
else if((r_state[1:0] == 2'b10) && (r_sec_cnt == 5'b0_0010)
r_state <= {r_state[2],2'b11};
else if((r_state[1:0] == 2'b11) && (r_sec_cnt == 5'b0_0010)
r_state <= {~r_state[2],2'b00};
else if(r_state[1:0] == 2'b01)
r_state <= 3'b000;
else
r_state <= r_state;
else
r_state <= r_state;
end
end
................................

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Answer 2

module traffic(clk,urgency,east_west,south_north,led);
input clk;
input urgency;
output [7:0]east_west,south_north;
output [5:0]led;
reg [7:0]east_west,south_north;
reg [5:0]led;
initial begin
east_west<=8'b0;
south_north<=8'b0;
led<=6'b100001;end
always @(posedge clk)
begin if(urgency==1) led<=6'b100100;
else if(east_west==8'b0 && south_north==8'b0) begin
east_west<=8'b00101101;
south_north<=8'b00101000;
led<=6'b100001;end
else if(east_west==8'b00000110 && south_north==8'b1) begin
east_west<=8'b00000101;
south_north<=8'b00000101;
led<=6'b100010; end
else if(east_west==8'b1 && south_north==8'b1 && led[5]==1'b1) begin
east_west<=8'b00101000;
south_north<=8'b00101101;
led<=6'b001100; end
else if(east_west==8'b1 && south_north==8'b00000110) begin
east_west<=8'b00000101;
south_north<=8'b00000101;
led<=6'b010100;end
else if(east_west==8'b1 && south_north==8'b1 && led[2]==1'b1) begin
east_west<=8'b00101101;
south_north<=8'b00101000;
led<=6'b100001; end
else if(east_west[3:0]==4'b0000) begin
east_west<=east_west-8'b111;
south_north<=south_north-1'b1; end
else if(south_north[3:0]==4'b0000) begin
east_west<=east_west-1'b1;
south_north<=south_north-8'b111; end
else begin
east_west<=east_west-1'b1;
south_north<=south_north-1'b1;
end
end
endmodule