verilog中如何将二维存储器转为一维的数组并赋值，求大神帮忙！

Question

比如：
module pixel_interpolation(clk,rst,A,B,C,D,E,F,data_out);
input clk,rst,A,B,C,D,E,F;
output data_out;
reg [1:6] romb [1:6];
reg [1:36] data_in;
/*********************************data_initial***********************************/
integer i;
always @(posedge clk or negedge rst)
if(!rst)
begin
for(i=0;i<6;i=i+1)
romb [i] <= 6'b0;
data_in <= 36'b0;
end
else
$readmemb("ram.txt",romb);//读取ram里头的6X6数组。然后接下怎么赋值给data_in这个数组啊?
求大神帮忙！
谢谢！
又来麻烦你了！嘿嘿！

Answer 1

module pixel_interpolation(
input wire clk,
input wire rst_n,
input wire ram_cs, // Active high
input wire ram_wr_en,
input wire [2:0] ram_addr,
input wire [5:0] ram_din,
output reg [5:0] ram_dout,
output reg [35:0] ram_bits
);

parameter val_0 = 6'h11;
parameter val_1 = 6'h12;
parameter val_2 = 6'h13;
parameter val_3 = 6'h24;
parameter val_4 = 6'h25;
parameter val_5 = 6'h26;

// generate the ram memory
reg [5:0] mem [0:5];
wire ram_wr_act = ram_cs & ram_wr_en & (ram_addr<3'd6);
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin // set initial values here according to your need
mem[0] <= val_0;
mem[1] <= val_1;
mem[2] <= val_2;
mem[3] <= val_3;
mem[4] <= val_4;
mem[5] <= val_5;
end
else if(ram_wr_act ) mem[ram_addr] <= ram_din;
end

wire ram_rd_act = ram_cs & ~ram_wr_en & (ram_addr<3'd6);
always @(posedge clk or negedge rst_n) begin
if(~rst_n) ram_dout <= 6'h0;
else if( ram_rd_act) ram_dout <= mem[ram_addr];
end

// generate the ram_bits
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin // set initial values here according to your need
ram_bits[5:0] <= val_0;
ram_bits[11:6] <= val_1;
ram_bits[17:12] <= val_2;
ram_bits[23:18] <= val_3;
ram_bits[29:24] <= val_4;
ram_bits[35:30] <= val_5;
end
else if(ram_wr_act ) begin
case(ram_addr)
3'd0 : ram_bits[5:0] <= ram_din;
3'd1 : ram_bits[11:6] <= ram_din;
3'd2 : ram_bits[17:12] <= ram_din;
3'd3 : ram_bits[23:18] <= ram_din;
3'd4 : ram_bits[29:24] <= ram_din;
3'd5 : ram_bits[35:30] <= ram_din;
endcase
end
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