verilog 测试文件#200.1什么意思

Question

如题所述

Answer 1

module sim();

reg clk,rst,in;
wire out;

initial
begin
clk <= 0;
rst <= 0;
in <= 0;
#10
rst <= 1;
end

always #25 clk <= ~clk;本回答被网友采纳